ABSTRACT
The traditional tests are most expensive in terms of both test development costs and test implementation for analog and mixed signal circuits. In the commercial market, up to 80% of the test costs are due to the analog and mixed signal functions that typically occupy only around 10% of the chip area. So for testing the mixed signal ICs new testing strategies are investigated. In this paper, a novel test generation methodology for the detection of catastrophic faults in Digital to Analog converters (DAC) is proposed. The proposed fault oriented test generator computes the optimal test patterns based on genetic algorithm.
Keywords: Genetic algorithm (GA), catastrophic faults
1. INTRODUCTION
Digital to Analog converters are widely used in many commercial mixed signal ICs. Nowadays with the advances in technology the DAC of higher resolution like 16 bit, 20 bit, 24 bit converters are available in the market. With the growing usage of commercial mixed-signal ICs and systems, the need for economical, fast and accurate test methods is very high. Traditional test methods for analog and mixed signal circuits rely on specification testing, in which some or all response parameters are checked for the design specifications. However specification testing is time consuming and expensive. As an alternative, fault-based test strategies are being increasingly used. Fault-based techniques test for the presence or absence of physical manufacturing-related defects (faults), thereby providing a quantitative estimate of the effectiveness and completeness of the testing process. This will significantly impact the test development costs for an analog and mixed signal circuit and will decrease the time-to-market of a chip. Finally, the short duration and the easy-to-apply feature of the test patterns will lead to significant reduction in production test.
Similar to stuck-at fault models in digital circuits, hard fault modeling and simulation, which addresses analog and mixed signal circuits, have been a subject of many papers[1],[2],[3].In [2] the fault model for a transistor is implemented with surrounding switches and an optimization algorithm is used to find the test set. A fault can be modeled by opening and closing a switch. In [3] IDD measurements are used for the detection of hard faults. Here genetic algorithm is used for optimal test pattern generation.
A complete test generation method for fault detection has been implemented and tested. The paper is organized as follows: In Section 2 need for mixed signal testing is discussed. Section 3 introduces the fault models used in analog and mixed signal circuits. In Section 4 the basic concepts in test pattern generation are discussed. Section 5 presents an overview of the Genetic algorithm. The key test generation and optimization module is described in Section 6. Results are shown in Section 7.
2. Need for testing
For complex mixed signal integrated circuits, testing is one of the major cost factors in the over-all IC manufacturing costs. Basically it is impossible to realise 100% yield in semiconductor processing, therefore, testing has to be performed at various stages in the manufacturing flow. The aim is to identify all bad devices, defined as those that contain a fault or those that cause a functional failure.
3. FAULTS IN ANALOG AND MIXED SIGNAL CIRCUITS
At the defect level, an enormous number of different failures could be present and it is totally infeasible to analyze them as such. Thus failures are grouped together with regards to their logical fault effect on the functionality of the circuit and this leads to the construction of logical fault models as the basis for testing algorithms More precisely, a fault denotes the physical failure mechanism, the fault effect denotes the logical effect of a fault on a signal carrying net, and an error is defined as the condition (or state) of a system containing a fault (deviation from correct state). Faults can be further divided into classes as permanent faults, that is, fault in existence long enough to be observed at test time, as opposed to temporary faults (transient or intermittent), which appear and disappear in short intervals of time, or delay faults which affects the operating speed of the circuit.
Permanent faults are further classified into catastrophic (open and short) faults and parametric (due to disturbance in the process parameters) faults. When a catastrophic fault occurs, the topology of the circuit is changed. Parametric faults are also tested, because processing/layout disturbance is inherent in any manufacturing process. The performance parameters of each manufactured circuit will be deviated from the nominal one due to this and therefore corresponds to a different point in each parameter space. If it is within fault free space then circuit is treated as fault free, otherwise it is considered as faulty circuit.
4. TEST PATTERN GENERATION
In this section, some key concepts that are used in the rest of this paper are introduced. First the concept of automated test generation and its application to analog and mixed signal circuits is introduced. This is followed by a brief description of the fault models used in our approach.
4.1 Test generation for analog and mixed signal circuits
In any IC manufacturing process, the possibilities of occurrence of catastrophic (open and short) and parametric faults (variations in the process parameters) will be there, due to that there will be yield loss in the manufacturing unit. Testing methods based on specifications are time consuming and expensive. Testing techniques for analog and mixed signal blocks are gaining importance due to the difficulties involved in testing these blocks embedded in larger circuits. The analog blocks may not be directly accessible or all the nodes may not be accessible. So in recent years researchers are trying to apply the digital test techniques in analog and mixed signal domain. In this paper an automatic test generation method based on genetic algorithm is proposed which will result in optimum digital test pattern set.
4.2 Fault models
In this work an 8 bit ladder type digital to analog converter is used. The fault models used are shown in table 1.
Table.1.Fault models
|
Component |
Fault model |
|
Resistor |
Open, short |
|
Capacitor |
Open, short |
|
Transistor |
Open drain, open source, short drain-source, short gate-drain, short gate-source |
5. GENETIC ALGORITHM
5.1 Generation
Genetic algorithms are stochastic search techniques based on the mechanism of natural selection and natural genetics. Genetic algorithms start with an initial set of random solutions called population. Each individual in the population is called a chromosome. A chromosome is a string of symbols. The chromosomes evolve through successive iteration called generations.
5.2 Fitness
From the population individual strings are selected based on the fitness function to create next generation, called off springs. Off springs are formed by either (a) merging two chromosomes from current generation using a crossover operator or (b) modifying a chromosome using a mutation/inversion operator.
5.3 Cross over
Crossover is the main genetic operator. Simple crossover may proceed in two steps. First, members of the newly reproduced strings in the mating pool are mated at random. Second, each pair of strings undergoing crossing over chooses a random cut-point and generates the offspring by combining the segment of one parent to the other parent to the right of the cut-point.
5.4 Mutation
Mutation is used to avoid sub-optimal results. It is a background operator that produces spontaneous random changes in various chromosomes. A simple way to achieve mutation would be to alter one or more genes. The GA process starts with a random population and iterates until the termination condition is met.
6. TEST PATTERN GENERATION
 |
Fig.6.1 Test pattern generation using Genetic algorithm
Test pattern generation is the process of generating a (minimal) set of input patterns to stimulate the inputs of a circuit, such that detectable faults can be exercised (if present).
The key blocks of the proposed method is shown in Fig.6.1
Test generation
The test patterns are generated using genetic optimization technique such that the patterns detect maximum faults. The Digital patterns are applied through a DAC circuit. For each pattern a detection threshold is fixed using Monte Carlo simulation .The detection threshold is fixed as
µ f -µ ff >= 3(σ f – σ ff)
Where µ f , σ f - mean and standard deviation of faulty distribution
µ ff , σ ff – mean and standard deviation of fault free distribution
Fault simulation
Faults are simulated one by one; the output response is noted for each fault in the circuit. For each pattern all the faults are simulated.
Fitness calculation
For calculating the fitness a heuristics is used where more weight age is given for test vectors which detect the hard to detect faults in the circuit. The fitness Calculation of the vectors depends relatively on the other vectors. The vectors, which are detecting new faults that are not detected by other vectors, have more fitness value.
