The ever-increasing capabilities of VLSI have allowed including the complex analog and digital circuits in a single chip. With growing circuit integration, tomorrow’s challenge of microelectronics is the System on Chip (SoC). Such complex, mixed-signal and mixed-technology circuits impose to reconsider traditional design methods. Behavioral modeling is one key, to explore high-level architecture possibilities.  With HDLs, it is possible to simulate and synthesize the digital circuits. Behavioral level modeling of complex mixed signal VLSI circuits cannot be done with SPICE simulator. The solution for this is Analog hardware description language . Using VHDL-AMS language the high-level modeling of these circuits, which contains both analog and digital parts, can be described and simulated. The other problem in fault simulation of mixed signal circuits is simulation time. The proposed method reduces simulation time compared to SPICE simulation. In this paper system- level modeling of a Temperature controller chip and fault simulation of that circuit using the proposed method is described.

Keywords:

VHDL-AMS, Behavioral modeling, Structural modeling, mixed signal, Fault simulation, high-level modeling, system level modeling

INTRODUCTION

The exploding telecommunications market as well as markets for consumer and automotive electronics has resulted in rapidly increased number of mixed-signal devices being produced. In the production of mixed-signal circuits, test can be a limiting factor contributing significantly to manufacturing cost. Compared with digital testing, the lack of a systematic approach to mixed-signal testing development in the IC industry has resulted in a relatively poor test coverage, high-test costs, and long test-development time. In order to solve these problems, a structured test method called Defect-Oriented Testing (DOT) has been proposed for analogue circuits and studied in the recent years. The presented results in the literature show that DOT is a promising structural method to optimise test vectors with high fault coverage and low test-application costs[1],[2].

 However, there are still some problems like development of fault models, time taken for fault simulation are to be solved before this method can be used in the IC industry. The problem of reducing the fault simulation time is one of the most important issues hampering this application in industry. One solution to reduce the fault simulation time is to use high-level models in the fault simulation. In this approach, during fault simulation, the fault-free blocks are simulated with high-level models to reduce the simulation time. The faulty blocks are simulated at transistor level for easy and accurate injection of the faults.

BEHAVIORAL MODEL

The OP-AMP benchmark circuit[3] shown in Figure.1 is modeled in different configuarations at behavioral level.The simulation time for the circuit in the SPICE simulator and the behavioural level simulation is given in Table.1.It shows that the simulation time taken by behavioural models are less compared to SPICE models.

Table.1. Simulation Time Comparison

FAULT MODELS

At the defect level, an enormous number of different failures could be present and it is totally infeasible to analyze them as such. Thus failures are grouped together with regards to their logical fault effect on the functionality of the circuit, and this leads to the construction of logical fault models as the basis for testing algorithms More precisely, a fault denotes the physical failure mechanism, the fault effect denotes the logical effect of a fault on a signal carrying net, and an error is defined as the condition (or state) of a system containing a fault (deviation from correct state). Faults can be further divided into classes as permanent faults, that is, fault in existence long enough to be observed at test time, as opposed to temporary faults (transient or intermittent), which appear and disappear in short intervals of time, or delay faults which affects the operating speed of the circuit.

The OP-AMP benchmark circuit[3] as shown in Figure.1 is taken as device under test and the circuit and faults are modeled at behavioral level.The Catastrophic fault models considered for the The MOS transistor are 1. Open source 2.open drain 3. Source-drain short 4.gate-source short 5.gate-drain short. For resistors and capacitors open and short faults are used. Stuck-open fault can be simulated by adding high resistance in series with (100Mohms) the component to be faulted. Stuck-short fault can be simulated by connecting a small resistor in parallel (1ohm) with the component.

All the catastrophic faults are modeled behaviouraly.Behavioural level fault model done for M10 transistor source and drain short fault using the equations is shown in Figure.2.

Fig.2 Behavioural model of M10 Transistor fault

SYSTEM LEVEL MODELING

VHDL-AMS language supports various domains like Mechanical, Thermal and Hydraulic. A temperature controller circuit was modeled behaviorally.The controller was modeled for following specifications. If the temperature range is in between –20 to +10 degree Celsius then output indicates “L” high, if the temperature range is 10 to 30 degree Celsius then the output indicates “N” high, and If the temperature more then 30 degree the output indicates “H” high. The overall system is shown in Figure.3; For this sensor model, the high precision temperature to voltage converter NCT47 was modeled. The minimum and maximum value of the output of sensor is 500 mV and 1.75 V. An amplifier is designed using the modeled opamp to amplify the output of sensor. The gain of the amplifier is fixed with 2.857. The output of the sensor is given to ADC. Simulated results are shown in Figure.4 and description level of the total system is given in Table.2.

When Temperature=300K L=’0’, N=’1’, H=’0’

FAULT SIMULATION OF TEMPERATURE CONTROLLER CHIP

 One solution to reduce the massive analogue fault-simulation time is to use high-level models. In this approach, during fault simulation, the fault-free blocks are simulated with high-level models to reduce the simulation time. At same time, the faulty blocks are simulated at transistor level for easy and accurate injection of the faults. A crucial issue for this method is the generation of the suitable high-level models of the fault-free blocks. Because the behavior of the faulty block is unknown and it is possible that it works totally different from the fault-free one, the high-level model used in fault simulations has different requirements as compared to the high-level models normally used in IC design.

 The approach has been applied to a temperature controller chip. In this modeling, amplifier module was considered as faulty, so it was developed at transistor level, and other modules are modeled behaviorally. Faults are injected in the amplifier module, and the simulation results are shown in Table.3.

Table: 3 Simulation results of Temperature controller chip under faulty conditions

In Table.3 Y-refers, that fault is detected and N-refers that fault is not detected. All the simulation times in Table.3 were obtained using Hamster 2.1 running on a pentium2 350MHz PC with Windows NT.

CONCLUSION

In this work, modeling of operational amplifier and Temperature controller chip using the standard language VHDL-AMS was developed. In this method it was found that the simulation time is considerably reduced under different faulty conditions compared to SPICE level simulation.

REFERENCE: 

[1]: Milor & Visvanathan, “Detection of catastrophic faults in analogue integrated circuits”, IEEE Trans. on Computer Aided Design (CAD), 8, 2, 1989, pp114-130.

[4]: B. Kaminska, K. ArabiSoma “Analog and Mixed-Signal Benchmark Circuits”– First Release,1997

[5]: IEEE Standard VHDL Analog and Mixed-Signal Extensions, IEEE Std 1076.1-1999.

 [6]: BEAMS, Behavioral modeling of analogue and Mixed Systems, a non-lucrative association

        for the promotion of behavioral modeling and simulation with languages,

        http://www.beams.asso.fr